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ds1742 y2kc nonvolatile timekeeping ram www.maxim-ic.com features pin configuration ? integrated nv sram, real-time clock, crystal, power-fail control circuit and lithium energy source 1 of 16 rev: 102808 ? clock registers are accessed identically to the static ram; these registers are resident in the eight top ram locations ? century byte register ? totally nonvolatile with over 10 years of operation in the absence of power ? bcd coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 ? battery voltage level indicator flag ? power-fail write protection allows for 10% v cc power supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? standard jedec bytewide 2k x 8 static ram pinout ? quartz accuracy 1 minute a month at +25c, factory calibrated ? underwriters laboratories (ul?) recognized ordering information part voltage (v) temp range pin-package top mark** ds1742-85 5.0 0c to +70c 24 edip (0.740a) ds1742-85 ds1742-85+ 5.0 0c to +70c 24 edip (0.740a) ds1742-85+ ds1742-100 5.0 0c to +70c 24 edip (0.740a) ds1742-100 ds1742-100+ 5.0 0c to +70c 24 edip (0.740a) ds1742-100+ ds1742-100ind 5.0 -40c to +85c 24 edip (0.740a) ds1742-100ind ds1742-100ind+ 5.0 -40c to +85c 24 edip (0.740a) ds1742-100ind+ DS1742W-120 3.3 0c to +70c 24 edip (0.740a) DS1742W-120 DS1742W-120+ 3.3 0c to +70c 24 edip (0.740a) DS1742W-120+ ds1742w-150 3.3 0c to +70c 24 edip (0.740a) ds1742w-150 ds1742w-150+ 3.3 0c to +70c 24 edip (0.740a) ds1742w-150+ + denotes a lead(pb)-free/rohs-compliant device. **the top mark will include a ?+? on lead(pb)-free devices. ul is a registered trademark of underwriters laboratories, inc. v cc a8 a9 we oe a10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 gnd 12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 24 23 22 21 20 19 18 17 16 15 14 13 ds1742 top view encapsulated dip
ds1742 2 of 16 pin description pin name function 1 a7 2 a6 3 a5 4 a4 5 a3 6 a2 7 a1 8 a0 19 a10 22 a9 23 a8 address input 9 dq0 10 dq1 11 dq2 13 dq3 14 dq4 15 dq5 16 dq6 17 dq7 data input/output 12 gnd ground 18 ce active-low chip-enable input 20 oe active-low output-enable input 21 we active-low write-enable input 24 v cc power-supply input description the ds1742 is a full-function, ye ar 2000-compliant (y2kc), real-time clock/calendar (rtc) and 2k x 8 nonvolatile static ram. user access to all registers within the ds1742 is accomplished with a bytewide interface as shown in figure 1. the rtc information and control bits reside in the eight uppermost ram locations. the rtc regist ers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour bcd fo rmat. corrections for the day of the month and leap year are made automatically. the rtc clock registers are double-buffered to av oid access of incorrect data that can occur during clock update cycles. the double-buffered system also prevents time loss as the timekeeping countdown continues unabated by acce ss to time register data. the ds1742 also contains its own power-fail circuitry, which deselects the device when the v cc supply is in an out-of-tolerance condition. th is feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided.
ds1742 3 of 16 clock operations?r eading the clock while the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the ds1742 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the inte rnal clock register updating process does not affect clock ac curacy. updating is halt ed when a 1 is written into the read bit, bit 6 of the century register, see table 2. as l ong as a 1 remains in that position, updating is halted. after a halt is issued, the registers reflec t the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the ds17 42 registers are updated simultaneously after the internal clock register updating process has been re-enabled. updating is within a second after the read bit is written to 0. the read bit must be a zero for a minimum of 500 ? s to ensure the external registers will be updated. figure 1. ds1742 block diagram table 1. truth table v cc ce oe we mode dq power v ih x deselect high-z x standby v il x v il write data in active v il v il v ih read data out active v cc > v pf v il v ih v ih read high-z active v so < v cc < v pf deselect cmo dby x x x high-z s stan v cc < v so < v pf x x x deselect high-z data retention mode
ds1742 4 of 16 setting the clock as shown in table 2, bit 7 of t he century register is the write bi t. setting the write bit to a 1, like the read bit, halts updates to the ds1742 registers. the user can then load them with the correct day, date and time data in 24-hour bcd format. resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. stopping and starting the clock oscillator the clock oscillator may be stopped at any time. to increase the s helf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb (bit 7) of the seconds registers, see table 2. setti ng it to a 1 stops the oscillator. frequency test bit as shown in table 2, bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic 1 and the oscillator is running, t he lsb of the seconds regi ster will toggle at 512 hz. when the seconds register is being read, the dq0 line will toggle at the 512 hz frequency as long as conditions for access remain valid (i.e., ce low, low, oe we high, and address for seconds register remain valid and stable). clock accuracy the ds1742 is guaranteed to keep time accuracy to within 1 minute per month at 25c. dallas semiconductor calibrates the rtc at the fact ory using nonvolatile tuning elements. the ds1742 does not require additional calibration. for this reason, methods of field clock calibration are not available and not necessary. clo ck accuracy is also affected by the electrical environment and caution should be taken to place the rtc in the lowest level emi section of the pcb layout. for additional informa tion refer to application note 58. table 2. register map data addres s b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function range 7ff 10 year year year 00?99 7fe x x x 10 month month month 01?12 7fd x x 10 date date date 01?31 7fc bf ft x x x day day 01?07 7fb x x 10 hour hour hour 00?23 7fa x 10 minutes minutes minutes 00?59 7f9 osc 10 seconds seconds seconds 00?59 7f8 w r 10 century century control 00?39 osc = stop bit r = read bit ft = frequency test w = write bit x = see note below bf = battery flag note: all indicated ?x? bits are not used but must be set to ?0? during write cycle to ensure proper clock operation.
ds1742 5 of 16 r retrieving data from ram or clock the ds1742 is in th e read mode wheneve oe (output enable) is low, we (write enable) is high, and ce (chip enable) is low. the device architec ture allows ripple-through access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the c e and oe access times and states are satisfied. if or ce oe access times and states are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by , and ce oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the ds1742 is in the write mode whenever and we ce are in their active state. the start of a write is referenced to the latter occurring transition of on ce we . the addresses must be held valid throughout the cycle. or ce we must return inactive for a minimum of t wr prior to the initiation of another r ead or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typi cal application, the oe signal will be hi gh during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if is low prior to oe we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then disable the outputs t wez after goes active. we data retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the pow er fail point, v pf , (point at which write protection occurs) the internal clock registers and sr am are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are main tained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power fail point, v pf , access to the device is inhibited. if v pf is less than vso , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than vso , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below vso . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels.
ds1742 6 of 16 battery longevity the ds1742 has a lithium power source that is designed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. t he capability of this internal power supply is sufficient to power the ds1742 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at 25c with the internal clock oscill ator running in the absence of v cc power. each ds1742 is shipped from dallas semiconductor with its lith ium energy source disc onnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1742 will be much longer than 10 years since no lithi um battery energy is consumed when v cc is present. battery monitor the ds1742 constantly monitors the battery voltage of the internal battery . the battery flag bit (bit 7) of the day register is us ed to indicate the voltage level range of the battery. this bit is not writable and should always be a 1 when read. if a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable.
ds1742 7 of 16 absolute maxi mum ratings voltage range on any pin relative to ground??????????????..-0.3v to +6.0v storage temperature range? ????????????????????...-40c to +85c soldering temperature (e dip, leads)..????????..+260 ?c for 10 seconds (see note 7) this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specif ication is not implied. exposure to absolute ma ximum rating conditions for extended periods of time may affect reliability. operating range range temperature v cc commercial 0c to +70c (noncondensing) 3.3v ? 10% or 5v ? 10% industrial -40c to +85c (nonco ndensing) 3.3v 10% or 5v 10% recommended dc oper ating conditions (over the operating range) parameter symbol min typ max units notes v cc = 5v 10% v ih 2.2 v cc + 0.3v v 1 logic 1 voltage (all inputs) v cc = 3.3v 10% v ih 2.0 v cc + 0.3v v 1 v cc = 5v 10% v il -0.3 +0.8 v 1 logic 0 voltage (all inputs) v cc = 3.3v 10% v il -0.3 +0.6 v 1 dc electrical characteristics (v cc = 5.0v ? 10%, over the operating range.) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 1 3 ma 2, 3 cmos standby current ( ce ? ?v cc - 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1ma) v ol 0.4 1 write protection voltage v pf 4.25 4.50 v 1 battery switchover voltage v so v bat 1, 4
ds1742 8 of 16 dc electrical characteristics (v cc = 3.3v ? 10%, over the operating range.) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current ( ce ? ?v cc - 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 1 output logic 0 voltage (i out =2.1ma) v ol 0.4 1 write protection voltage v pf 2.80 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 ac characteristics?read cycle (5v) (v cc = 5.0v ? 10%, over the operating range.) 85ns access 100ns access units parameter symbol min max min max read cycle time t rc 85 100 ns address access time t aa 85 100 ns to dq low-z t cel 5 5 ns ce access time t cea 85 100 ns ce data off time t cez 30 35 ns ce to dq low-z t oel 5 5 ns oe access time t oea 45 55 ns oe oe data off time t oez 30 35 ns output hold from address t oh 5 5 ns
ds1742 9 of 16 ac characteristics?read cycle (3.3v) (v cc = 3.3v ? 10%, over the operating range.) 120ns access 150ns access parameter symbol min max min max units read cycle time t rc 120 150 ns address access time t aa 120 150 ns to dq low-z t cel 5 5 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns ce to dq low-z t oel 5 5 ns oe access time t oea 100 130 ns oe oe data off time t oez 35 35 ns output hold from address t oh 5 5 ns read cycle timing diagram
ds1742 10 of 16 ac characteristics?write cycle (5v) (v cc = 5.0v ? 10%, over the operating range.) 85ns access 100ns access parameter symbol min max min max units write cycle time t wc 85 100 ns address access time t as 0 0 ns pulse width t wew 65 70 ns we ce pulse width t cew 70 75 ns data setup time t ds 35 40 ns data hold time t dh 0 0 ns address hold time t ah 5 5 ns we data off time t wez 30 35 ns write recovery time t wr 5 5 ns ac characteristics?write cycle (3.3v) (v cc = 3.3v ? 10%, over the operating range.) 120ns access 150ns access parameter symbol min max min max units write cycle time t wc 120 150 ns address setup time t as 0 0 ns pulse width t wew 100 130 ns we ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 40 50 ns write recovery time t wr 10 10 ns
ds1742 11 of 16 write cycle timing diagram? write-enable controlled write cycle timing diagram?chip-enable controlled
ds1742 12 of 16 power-up/power-down characteristics (5v) (v cc = 5.0v ? 10%, over the operating range.) parameter symbol min typ max units notes or ce we at v ih , before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc fall time: v pf(min) to v so t fb 10 ? s v cc rise time: v pf(min) to v pf(max) t r 0 ? s power-up recover time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5, 6 power-up/power-down waveform timing (5v device)
ds1742 13 of 16 power-up/power-down ch aracteristics (3.3v) (v cc = 3.3v ? 10%, over the operating range.) parameter symbol min typ max units notes or we ce at v ih , before power- down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s power-up recovery time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5, 6 power-up/power-down waveform timing (3.3v device) capacitance (t a = +25c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf capacitance on all output pins c o 10 pf
ds1742 14 of 16 ac test conditions output load: 100pf + 1ttl gate input pulse levels: 0.0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltage referenced to ground. 2) typical values are at 25c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lo wer of either the battery voltage or v pf . 5) data retention time is at 25c. 6) each ds1742 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 7) real-time clock modules can be successfu lly processed through conventional wave- soldering techniques as long as temperature exposure to the lithium energy source contained within does not exce ed +85c. post-solder cleaning with water washing techniques is acceptable, provid ed that ultrasonic vibration is not used to prevent damage to the crystal.
ds1742 15 of 16 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 24 edip mdf24+1 21-0245
ds1742 16 of 16 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. revision history revision date description pages changed added ?ul recognized? bullet to features and new ordering information table. 1 added new pin description table. 2 updated note for table 2 4 041305 updated operating tem perature range for absolute maximum ratings . 7 071905 corrected 24-pin to 28-pin package and top mark items in ordering information table. 1 060706 removed reference to j-std-020 and indicated the lead soldering temperature of +260 ? c for 10 seconds max. 7 022207 added ds1742-85, ds1742-85+ to the ordering information table; removed ds1742p- 100+ (powercap) package. 1 102808 removed the ?70 orderi ng numbers from the ordering information table. 1

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